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Chapter 2: Getting Started
Simulate the Design
4. Click on Tcl Console under Utility_Windows (View menu).
5. In the Tcl console window, type:
source <variation name> _constraints.tcl
To run the Tcl script in a UNIX or Linux operating system terminal, type:
cd..<project_directory>
quartus_sh -t <variation name> _constraints.tcl
Depending on the type of constraints applied by the Tcl script, analysis and synthesis
may be run twice. For example, if hierarchy independent constraints are needed, the
Tcl script runs analysis and synthesis before applying the constraints. Therefore, when
you run a full compilation, after running the Tcl script, the analysis and synthesis are
run a second time.
You can now integrate your custom MegaCore function variation into your design,
simulate, and compile.
Simulate the Design
You can simulate your design using the generated VHDL and Verilog HDL IP
functional simulation models.
f For more information on IP functional simulation models, refer to the Simulating
Altera also provides a Verilog HDL demonstration testbench, including scripts to
compile and run the demonstration testbench using a variety of simulators and
models. This testbench demonstrates the typical behavior of an 8B10B MegaCore
function, and how to instantiate a model in a design. The demonstration testbench
does not perform any error checking.
f For a complete list of models or libraries required to simulate the 8B10B
Encoder/Decoder MegaCore function, refer to the _ run_modelsim.tcl scripts
provided with the demonstration testbench.
IP Functional Simulation Model
To use the demonstration testbench with IP functional simulation models in the
ModelSim ? simulator, follow these steps:
1. Start the ModelSim simulator.
2. From the ModelSim File menu, use Change Directory to change the working
directory to the directory where you created your 8B10B Encoder/Decoder
variation.
3. In the ModelSim Transcript window, execute the command
do <variation_name>_run_modelsim.tcl which sets up the required libraries,
compiles the netlist files, and runs the testbench. The ModelSim Transcript
window displays messages from the testbench reflecting the results of the
simulation.
8B10B Encoder/Decoder MegaCore Function User Guide
May 2011 Altera Corporation
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